Pre-driver circuits are typically required in transmitters used in high speed signaling systems such as high speed serializer/deserializer (serdes) based systems. The reason such pre-driver circuits are required is essentially twofold. First, pre-driver circuits provide an optimal input common-mode voltage level to their associated driver circuits, thereby improving the signal quality of the driver circuits and hence the encompassing transmitters. Second, pre-driver circuits allow nominal (i.e., low voltage) devices to be used for the driver circuits. That is, lower voltage devices typically exhibit lower capacitance, and thus typically allow higher-speed driver circuits and encompassing transmitters. However, lower voltage devices typically have lower gate-stress tolerance. Pre-driver circuits can alleviate this gate-stress problem by providing a level-shifting function, which also allows the pre-driver circuits to operate off a supply voltage that is smaller than the supply voltage used by the driver circuits.
Referring to FIG. 1, there is shown a conventional differential transmitter 100 comprising a pre-driver circuit 102 and a driver circuit 104. The pre-driver circuit 102 comprises a differential transistor pair 106, a pair of resistive loads 108, and a current source 110. The driver circuit 104 comprises a differential transistor pair 114, a pair of resistive loads 116, and a current source 120. The supply voltage (Vdd) used by the pre-driver circuit 102 is smaller than the supply voltage (Vtt) used by the driver circuit 104.
To allow the transmitter 100 to operate at high speeds (e.g., 3 Gigahertz and above), the pre-driver circuit 102 must operate fast enough such that it does not limit the bandwidth of the transmitter 100. That is, the pre-driver circuit 102 must operate such that the combination of the rise time (Trise) and the fall time (Tfall) in the pre-driver circuit 102 must be less than the bit time (Tbit) associated with the operating frequency. Also, the outputs from the pre-driver circuit 102 should always reach the respective voltage rails to avoid data-dependent jitters. However, as shown in FIG. 1, a parasitic capacitance (C) 112 is always present at the outputs of the pre-driver circuit 102. This parasitic capacitance (C) 112 can cause significant delays in the rise time (Trise) and the fall time (Tfall) in the pre-driver circuit 102. Furthermore, the product of the current (Ipr) drawn by the current source 110 and the load resistance (R) 108 needs to be sufficient to produce enough voltage swing to switch the driver circuit 104. Additionally, the product of the current (Ipr) drawn by the current source 110 and the load resistance (R) 108 cannot be too large to present a gate-stress problem to the driver circuit 104.
Given the above-mentioned considerations, several solutions have been proposed to increase the speed of the pre-driver circuit 102, and hence the transmitter 100. For example, referring to FIG. 2, there is shown a single-ended shunt-peaked amplifier circuit 200 that can be duplicated and used in the differential pre-driver circuit 102 of FIG. 1. The shunt-peaked amplifier circuit 200 comprises an input transistor 202, a resistive load 204, an inductive load 206, and a parasitic capacitance 208. The primary benefit of the shunt-peaked amplifier circuit 200 is the inclusion of the inductive load 206, which delays current flow through the resistive load 204 so as to allow the parasitic capacitance 208 to discharge more quickly than if the inductive load 206 was not present.
Referring to FIG. 3, there is shown an equivalent model 300 of the shunt-peaked amplifier circuit 200 of FIG. 2, which indicates how the inductive load 206 delays current flow through the resistive load 204 so as to allow the parasitic capacitance 208 to discharge more quickly than if the inductive load 206 was not present.
Referring to FIG. 4, there is shown a differential pre-driver circuit 400 incorporating the single-ended shunt-peaked amplifier circuit 200 of FIG. 2. The differential pre-driver circuit 400 comprises a differential transistor pair 402, a pair of resistive loads 404, a pair of inductive loads 406, and a current source 408. The benefit of the pre-driver circuit 400 of FIG. 4 as compared to the pre-driver circuit 102 of FIG. 1 is the inclusion of the pair of inductive loads 406, which delay current flow through the pair of resistive loads 404 so as to allow parasitic capacitances 410 to discharge more quickly than if the pair of inductive loads 406 were not present.
While the pre-driver circuit 400 of FIG. 4 may operate at higher speeds than the pre-driver circuit 102 of FIG. 1, the pair of inductive loads 406 consume a relatively large amount of area, which often translates into increased cost and decreased performance per unit area.
In view of the foregoing, it would be desirable to provide a technique for increasing the speed of a pre-driver circuit, and hence a corresponding transmitter, which overcomes the above-described inadequacies and shortcomings.